1. Field of the Invention
In the information technology field, there is at the present time a tendency for central processing units to have an increasingly complex structure, because of continually increasing processing power objectives.
2. Brief Description of the Invention
In order to increase this last parameter, up till now it has been proposed, firstly, to insert between the central processing unit, such as a microprocessor, and the random access memory, a cache memory the access time of which is very much lower than the access time of the random access memory, often in a ratio of 10. As has been shown moreover in FIG. 1a, the cache memory is in fact subdivided into an instruction cache memory CI and a data cache memory CD, or addresses, each interconnected by a BUS link with the random access memory through a controller for example. Other link units such as controller or universal synchronous-asynchronous receiver-transmitters, USART, are interconnected with the BUS link so as to enable the central processing unit to start communicating.
Secondly, in order to further increase processing power, multilevel microprocessor structures have been proposed.
In the context of the disclosure of the object of the present invention, the notion of multiprocessors structure is not restricted to a given number of microprocessors, a monoprocessor structure, such as shown FIG. 1a, being also included in this notion. As a result, the terms microprocessor and micro-controller structure, directed to comprise one or more microprocessors, will be used without distinction.
These multiple structures, as shown for example in FIG. 1b, can include successively:
a general BUS, BUS.sub.0, with which is interconnected by means of a controller a main memory, RAM.sub.0, shared by the different microprocessors; PA1 a plurality of microprocessor aggregates, each aggregate A.sub.1 to A.sub.3 comprising a specified number of microprocessors, being, clearly, interconnected to the general BUS and to the main memory by means of a controller; PA1 an intercommunication conflict manager circuit, ARB.sub.0, having a tree structure and directly interconnected to the controller, CNTRL, of each aggregate. PA1 a main field comprising a useful data word encoded on N bits communicated by the master component to the slave component; PA1 an auxiliary field encoded on p bits, this auxiliary field comprising at least one operation code field enabling identification of the instruction message and a signature field enabling identification of the master component and the slave component addressee of this instruction message as well as the transaction occurring between this master component and this slave component, and, on a clock cycle following the current clock cycle: PA1 a proof of transmission message field from the master component to the slave component and an acknowledgement message field from the slave component to the master component, the true value of the proof of transmission message and the true value of the acknowledgement message enabling validation of a partial transaction between the master component and the slave component, each master or slave component interconnected with each BUS link comprising in addition: PA1 a first and a second transmission register of instruction messages and a reception register of instruction messages, which makes it possible to ensure from each master or slave component the successive transmission of instruction messages on successive clock cycles to an addressee slave or master component, in accordance with a succession of partial transactions constituent of one transaction.
Generally, as will be seen moreover in FIG. 1b, the structure of each aggregate approximately reproduces that of the multiprocessors structure, relative to the aggregates, in so far as each aggregate is located around a local BUS BUS.sub.1 to BUS.sub.3 to which all the components of the aggregate under consideration are interconnected. As can be seen in FIG. 1b, any microprocessor of a specified aggregate is therefore interconnected, by means of a first cache memory, subdivided for example into instruction cache memory and data cache memory as shown in FIG. 1a, to the local BUS of the corresponding aggregate, which, by means of a controller, is interconnected to the general BUS, BUS.sub.0. Each aggregate also includes a second cache memory RAM.sub.1 to RAM.sub.3 directly connected to the controller of the aggregate, the first cache memory of each microprocessor constituting a first level cache memory and the second cache memory a second level cache memory. Lastly, each aggregate includes a local intercommunication conflict manager circuit ARB.sub.1 to ARB.sub.3 also having a tree structure and interconnected to each first level cache memory of the corresponding aggregate.
The mode of operation of each constituent component of the multiprocessors structure, a component able to be constituted either by a constituent component of an aggregate, or by an aggregate itself or again by the main memory, is managed by an intercommunication protocol, complex, in which hierarchical or priority levels are allocated to each aforementioned component. Clearly it is understood that the number of hierarchical levels, general BUS, local BUS, is not moreover limited to two, as shown in FIG. 1b, a hierarchical level being associated with all the components interconnected to a local general BUS, several hierarchical levels of local BUS being conceivable in very complex structures.
Contrary to conventional BUS link systems used in known micro-controller architectures, such as MOTOROLA'S MC68000, in which the BUS link is blocked during the whole transaction time, in read or write mode, the intercommunication protocol for all the components is a protocol known in English by the term "split cycle", in which data packets are transmitted, the messages relative to the addresses and to the data being different and the data messages, particularly, being of different length, so as to enable maximum reduction in standby times, during which no message is transmitted on the BUS links.
The different length of the data messages entails, of necessity, predictive type intercommunication conflict risk management by the different intercommunication conflict manager circuits provided throughout the multiprocessors structure. Whatever the circumstances are, each intercommunication conflict manager circuit must, in order to empower any component placed under its authority, with which the latter is therefore interconnected, wait for any variable length data message transmission to be validated. For a more detailed description of a comparable mode of operation, reference can usefully be made to U.S. Pat. No. 5,265,635 enclosed within this specification as a reference. Such a mode of operation, complex, does make it possible to reduce standby and absence of message transmission by BUS times to the minimum, and therefore, in so doing, to optimise the logic pass band of this BUS link, at least for the longest data messages.
For a recapitulation of the main solutions brought to the management of conflicts of access and intercommunication between the different components of multiprocessors structures, reference can usefully be made to the work published by Kai Hwang, University of Southern California, and Faye, Rice University, entitled "Computer Architecture and Parallel Processing", McGraw-Hill Book Company, pp.480 to 487.